The present invention relates to a semiconductor memory device and timing control method for a semiconductor memory device, and more specifically, to a semiconductor memory device including a control circuit for controlling the timing for amplifying a data signal.
Semiconductor memory devices of recent years have seen increasing integration and higher operation speeds. Differences that arise during the manufacturing process of semiconductor memory devices lead to deviation in operation timings in circuits. Therefore, it is necessary to ensure the proper operation timing by taking into consideration the differences arising from the manufacturing process.
When data is read from the memory cell of a semiconductor memory device, a sense amplifier is activated after the signal amplitude of a bit line or data bus becomes large enough. Each circuit of a semiconductor memory device is affected by differences arising from the manufacturing process. To compensate for improper functioning of a sense amplifier caused by such differences, there is a predetermined margin for the activation time of the sense amplifier.
Japanese Laid-Open Patent Publication No. 2002-109887 describes an example of a semiconductor memory device provided with a delay circuit, which includes an inverter circuit. The delay circuit generated a signal for activating a sense amplifier. The delay circuit delays the timing for activating the sense amplifier so that the sense amplifier functions properly.
FIG. 1 shows the circuit configuration of a conventional semiconductor memory device 1.
The semiconductor memory device 1 includes a memory cell array 11, a word line driver 12, a column switch 13, a write amplifier 14, a sense amplifier 15, an input circuit 16, an output circuit 17, and a timing control circuit 18.
A plurality of memory cells 21 are arranged in the memory cell array 11. Each memory cell 21 is connected to the word line driver 12 through a word line WL, and connected to the column switch 13 through bit lines (bit line pair BL/XBL). The word line driver 12 selects one of a plurality of word lines WL based on an address. The column switch 13 receives a selection signal SEL from the timing control circuit 18 and connects a certain bit line BL and XBL to the write amplifier 14 or sense amplifier 15 based on the selection signal SEL.
Address, clock, and control signals are provided to the timing control circuit 18. The timing control circuit 18 executes timing controls necessary for accessing data stored in the memory cells 21 based on the address, clock, and control signals. The timing control circuit 18 has a delay circuit 18a, which includes a plurality of inverter circuits. The delay circuit 18a provides an activation signal STA to the sense amplifier 15.
FIGS. 2A and 2B are operation waveform diagrams of the semiconductor memory device 1 shown in FIG. 1.
As shown in FIG. 2A, when a word line WL is selected by the word line driver 12 (the word line WL is activated at high (H) level), the bit lines BL and XBL are driven based on the data stored in the memory cell 21. Thereafter, the electric potential of either the bit line BL or XBL (potential of the bit line XBL in FIG. 2A) is gradually reduced to ground level from the high-potential level of a power supply voltage VDD. When a predetermined time elapses after the activation of the word line WL, the timing control circuit 18 provides the activation signal STA to the sense amplifier 15. More specifically, the activation signal STA of the sense amplifier 15 is raised from low (L) level to high (H) level at a timing obtained by adding a predetermined margin to timing t1 at which the potential of the bit line XBL is sufficiently reduced to allow accurate reading of data. Then, the high activation signal STA activates the sense amplifier 15 to amplify the difference in the potential of the bit lines BL and XBL and read the data of the corresponding memory cell 21.
In the prior art, a self-timing type RAM has been proposed. As shown in a semiconductor memory device 2 of FIG. 3, the self-timing type RAM is provided with dummy circuits (circuits such as a dummy word line DWL, a dummy cell 22, dummy bit lines DBL and XDBL) to eliminate operation margins and absorb the manufacturing process differences of various circuits such as the word line WL, the memory cell 21, and the bit lines BL and XBL. In the semiconductor memory device 2, the dummy circuits operate in the same manner as normal circuits (circuits such as the word line WL, the memory cell 21, the bit line pair BL and XBL). The dummy circuit provides a dummy signal to a dummy timing control circuit 20.
The dummy timing control circuit 20 includes, for example, an inverter circuit, and provides the timing control circuit 18 with a self-reset signal STCLK, which corresponds to the level of the dummy signal. The timing control circuit 18 generates an activation signal STA based on the self-reset signal STCLK and activates the sense amplifier 15 with the activation signal STA.
FIGS. 4A and 4B are operation waveform diagrams of the semiconductor memory device 2 shown in FIG. 3.
As shown in FIG. 4A, when the word line WL is selected, the potential of one of the bit line pairs BL and XBL (potential of the bit line XBL in FIG. 4A) is gradually reduced to the ground level from the high-potential level of a power supply voltage VDD based on the memory data of the memory cell 21. Since the dummy word line DWL is also selected at the same time as the word line WL, the potential of the dummy bit line XDBL is also gradually reduced to ground level from the level of the power supply voltage VDD. When the potential of the dummy bit line XDBL becomes lower than a threshold voltage value Vth (more specifically, the threshold voltage of an inverter circuit in the dummy timing control circuit 20), the dummy timing control circuit 20 provides the timing control circuit 18 with a high self-reset signal STCLK. The timing control circuit 18 then provides the sense amplifier 15 with a high activation signal STA in response to the self-reset signal STCLK to activate the sense amplifier 15.